The present invention relates to the manufacture of electronic devices, particularly semiconductor devices, such as logic circuits, memory circuits, and/or combinations thereof.
Electronic devices are being made that combine various types of circuits on a single chip of semiconductor material. For example, devices are being made that combine logic circuits with memory arrays, or various types of memory, so that higher functionality can be achieved on a single chip. This type of integration often provides lower cost, smaller size and improved reliability compared to achieving the same functionality with a number of different chips wired together. Unfortunately, it can be difficult to integrate the manufacture of one type of circuit with another on a single chip.
Different types of circuits might have different types of devices that require different voltage inputs, and that have different thickness of gate oxide. For example, a logic field-effect transistor (“FET”) might have a different gate oxide thickness than an electronically erasable-programmable read only memory cell, or than a dynamic read-addressable memory (“DRAM”) cell. It is generally desirable to make all the gate oxides for all the devices on the chip in a single process step; therefore, it may be necessary to make the gate oxide in some regions thinner than the gate oxide in other regions.
A technique has been used to vary the thickness of an oxide layer grown on a silicon wafer during a oxide growth process by implanting nitrogen into selected regions of the silicon. The implanted nitrogen retards the growth of silicon oxide, resulting in a gate oxide of diminished thickness where the nitrogen was implanted. However, implanting nitrogen can degrade the resultant quality of the gate oxide. Gate oxide quality is especially important, compared to an inter-metal dielectric layer, for example, because of the electric field gradients a gate oxide must withstand and the low current leakage that is generally desired for good device performance. The quality of the gate oxide becomes even more important as device geometry and operating voltages shrink, both of which are associated with thinner gate oxides.
Therefore, it is desirable to fabricate an electronic device die with multiple thicknesses of gate oxide, and it is further desirable to be able to fabricate gate oxides of superior quality, especially thin gate oxides.